1. Field of the Invention
The present invention relates to a FIFO (First-In First-Out) buffer that transfers data between buses.
2. Description of Related Art
FIFO buffers are employed when data is transferred between buses. The FIFO buffers each store data transfer requests in order of receipt of the requests. The data transfer requests are executed by processing units. Accordingly, the data size of a single transfer request does not necessarily match the bus width. Additionally, in each FIFO buffer, the transfer requests that can be combined together have not been combined together. As a result, as the number of transfer requests increases, the number of access to buses increases. This hampers the improvement of the transfer efficiency.
FIG. 11 shows a configuration example of a FIFO device. A FIFO device 90 shown in FIG. 11 includes a FIFO buffer 91 that stores a write address, a FIFO buffer 92 that stores a write data strobe, and a FIFO buffer 93 that stores write data. The FIFO device 90 receives a write address, a write data strobe, and write data as transfer requests from a bus 14, and stores them respectively in the FIFO buffers 91 to 93. The FIFO device 90 outputs the stored transfer requests to a bus 15 in order of receipt of the transfer requests.
The FIFO device 90 shown in FIG. 11 sequentially transfers the transfer requests from the bus 14 to the bus 15. As a result, when the transfer requests are sequentially transferred to the bus 15, a load is likely to be imposed on the bus.
Japanese Unexamined Patent Application Publication No. 2002-149591 discloses a technology for optimizing the bus utilization for data read transfer and data write transfer. In the technology disclosed in Japanese Unexamined Patent Application Publication No. 2002-149591, the type of data transfer is determined, and data is asynchronously transferred between buses in a device using a FIFO according to the determined transfer type. According to the technology, however, data items to be stored in the FIFO are not combined together.
Further, Japanese Unexamined Patent Application Publication Nos. 2006-4340, 2000-132497, and 63-292356 each disclose a technology for reducing the number of data transfer operations to reduce a transfer time in direct memory access (DMA) data transfer. The DMA technology is premised on the use of consecutive data, and thus is hardly applied to a plurality of transfer requests received by a FIFO device.